1. Field of the Invention
This invention generally relates to testing of integrated circuit devices and more particularly to multiprobe testing of integrated circuit devices.
2. Relevant Background
Massive quantities of completely fabricated integrated circuits are functionally tested, i.e. probed in wafer form by a multiprobe test device before separation and encapsulation of the integrated circuits into individual packages. With considerations of cycle time in a capacity limited multiprobe area, a substantial number of the integrated circuits or chips are flagged as failures during this testing when, in fact, they are actually nominally acceptable chips.
This misdiagnosis is primarily caused by sporadic tester relay hang-ups or problematic test program sequencing and timing problems which are generally inherent in the multiprobe test equipment. The multiprobe test equipment includes a large number of relays which must mechanically open or close electrical contacts during the test sequences. Operation of these relays is usually consistent and reliable. However, with any complex electromechanical system, there may develop, and indeed there are, intermittent contact hang-ups and partial connections which not only are hard to isolate, but may occur randomly and infrequently in any one relay.
These bogus chip failures are taken on as acceptable yield loss during mass production to avoid loss of test floor output from re-setup of a test machine to reprobe the affected wafers. In other words, these failures are accepted based on the costs in lost time of remounting the wafers and retesting these chips.
However, this yield loss is cumulatively costly. The only option has been to hold the affected lot of wafers if yields were low enough to be held for yield analysis until failed chips could be found unverifiable. Then the selected wafers were sent back for resetup and reprobing. This course of action is time intensive and greatly increases multiprobe cycle time. Only wafers with greater than 7% failures are conventionally typically reprobed, due to capacity limitations.
Therefore there is a need for a method of automatically retesting failed chips without having to reset the wafer and reposition the multiprobe.